1. Field of the Invention
The present invention relates to a method for multilevel programming of phase change memory cells and to a multilevel phase change memory device.
2. Description of the Related Art
As is known, phase change memories use a class of materials that have the property of switching between two phases having distinct electrical characteristics, associated with two different crystallographic structures of the material: an amorphous, disorderly phase, and a crystalline or polycrystalline, orderly phase. The two phases are hence associated to resistivities of considerably different values.
Currently, the alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can be used advantageously in phase change memory cells. The currently most promising chalcogenide is formed from an alloy of Ge, Sb and Te (Ge2Sb2Te5), which is now widely used for storing information on overwritable disks and has been also proposed for mass storage.
In chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa.
Phase change can be obtained by locally increasing the temperature. Below 150° C., both phases are stable. Starting from an amorphous state, and raising the temperature above 200° C., there is a rapid nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change and becomes crystalline. To bring the chalcogenide back to the amorphous state it is necessary to raise the temperature above the melting temperature (approximately 600° C.) and then rapidly cool off the chalcogenide.
Memory devices exploiting the properties of chalcogenic material (also called phase change memory devices) have been already proposed.
The composition of chalcogenides suitable for the use in a phase change memory device and a possible structure of a phase change element is disclosed in a number of documents (see, e.g., U.S. Pat. No. 5,825,046).
As discussed in US-A-2003/0185047, a memory element of a phase change memory device comprises a chalcogenic material and a resistive electrode, also called a heater.
In fact, from an electrical point of view, the crystallization temperature and the melting temperature are obtained by causing an electric current to flow through the resistive electrode in contact or close proximity with the chalcogenic material and thus heating the chalcogenic material by Joule effect.
In particular, when the chalcogenic material is in the amorphous, high resistivity state (also called the reset state), it is necessary to apply a voltage/current pulse of a suitable length and amplitude and allow the chalcogenic material to cool slowly. In this condition, the chalcogenic material changes its state and switches from a high resistivity to a low resistivity state (also called the set state).
Vice versa, when the chalcogenic material is in the set state, it is necessary to apply a voltage/current pulse of suitable length and high amplitude so as to cause the chalcogenic material to switch to the amorphous phase.
As already mentioned, the resistivity of phase change materials may vary several orders of magnitude upon switching between the fully set (crystalline) state to the fully reset (amorphous) state. A typical range, for example, is 1 mΩ*cm in the set state to 1000 mΩ*cm in the reset state. However, the resistivity of the amorphous chalcogenic material is not stable and continuously increases according to a sub-linear law after phase transition. Thus, a quite rapid resistivity drift may take place, especially when large extensions of chalcogenic material are brought to the amorphous state.
The resistivity drift would not normally cause major problems in conventional two-level phase change memory cells, since the gap between the set state and the reset state is increased as well. Multilevel programming, instead, is not compatible with the resistivity drift, at present. According to conventional programming methods, in fact, every time a programming cycle is started, phase change memory cells are first brought to the fully crystalline state and then partially amorphized through a single voltage or current pulse, which lasts until a desired intermediate resistivity level is achieved. In this manner, however, large amorphous regions are still created, which are subjected to resistivity drift. The gap between the intermediate programming levels may not be kept constant and is narrowed on account of the resistivity drift. Thus, a sense amplifier associated with multilevel cells would fail to distinguish adjacent levels in a relatively short time after each phase transition. Moreover, the configuration of the large amorphous regions that are every time created greatly affects the resistivity level, but is not predictable. Thus, repeating identical programming cycles on the same phase memory change cell may lead to different resistivity levels.